The present invention relates generally to semiconductor memory devices, and, more particularly, to a semiconductor memory device which is capable of a higher speed of operation than presently available semiconductor memory devices.
As the integration density and memory capacity of semiconductor memory devices has increased, chip size has increased, and consequently, the interconnect lines for transporting data read from a selected memory cell thereof have become commensurately longer, all of which has ultimately caused delays in memory read operations. The net upshot is that the speed of operation of semiconductor memory devices has become increasingly limited by the signal delays over long interconnect lines having large voltage swings.
There has been widespread and extensive investigation throughout the semiconductor industry into the nature of the above-identified signal delay problem, and into the potential solutions to such signal delay problem. The following is a summary of the relevant findings that have been made thus far.
The signal delay is largely the result of large capacitive loads present along the long signal-transporting or interconnect lines which undergo large voltage swings. Using extended, e.g., multistage, line drivers helps to reduce such signal delay to some extent, but also creates problems with respect to the driver inputs. Moreover, multistage drivers increase power consumption and can actually lead to additional signal delays. Further, it is not feasible to use line drivers between the memory cells and bit lines of a semiconductor memory device.
Such signal delays due to long interconnect lines are being studied in terms of both voltage-mode and current-mode data signals. It has been observed that major speed improvements are achievable when current-mode data signals are used. The signal delay phenomenon for each type of signal mode will be described below, with the delay signal delay phenomenon for the voltage-mode signal being explained first.
FIG. 1 is an RC circuit network having an output load resistor R.sub.L. The voltage-mode signal delay .delta.t.sub.V can be expressed in terms of the following equation (1): EQU .delta.t.sub.V =R.sub.T C.sub.T /2(1+2R.sub.B /R.sub.T), (1)
where R.sub.T represents the total line resistance, C.sub.T represents the total line capacitance, and R.sub.B represents the internal resistance of the line driver.
From equation (1) it can be seen that when R.sub.B is greater than R.sub.T in a CMOS circuit, the signal delay will be considerably larger than the intrinsic line delay (R.sub.T C.sub.T /2). It can also be seen from equation (1) that the total line resistance R.sub.T has only a minor influence on the signal delay as long as R.sub.T is much greater than 2R.sub.B.
With continuing reference to FIG. 1, the current-mode signal delay will now be explained. It is assumed that the output of the signal-transport line is connected to a signal receiver having a low input resistance, thereby resulting in a low load resistance R.sub.L. The output signal is the current I.sub.0 flowing through the virtual short-circuit R.sub.L. This current signal is transferred to data output circuitry by a current-signal receiver.
Assuming an ideal virtual short circuit, i.e., R.sub.L =0, the ideal current-mode signal delay .delta.t.sub.i can be expressed in terms of the following equation (2): EQU .delta.t.sub.i =R.sub.T C.sub.T /2((R.sub.B +R.sub.T /3)/(R.sub.B +R.sub.T)). (2)
In contrast to the voltage-mode signal delay, the current-mode signal delay is approximately equal to the intrinsic line delay. Thus, the current-mode signal delay is much smaller than the voltage-mode signal delay.
However, the data line loads influence the speed of operation of a semiconductor memory device even if it is operated in the current mode.
The data sensing operation of a conventional semiconductor memory device will now be described in conjunction with FIG. 2, which depicts the data sensing circuitry of a conventional semiconductor memory device which is disclosed in Vol. 26, No. 4 of the IEEE Journal of Solid State Circuits (April, 1991). With reference to FIG. 2, the conventional data sensing circuitry includes a PMOS transistor P1 whose source electrode is coupoed to a power supply voltage (V.sub.DD), whose gate electrode is coupled to ground (V.sub.SS), and whose drain electrode is coupled to a bit line BL, a PMOS transistor P2 whose source electrode is coupled to the power supply voltage, whose gate electrode is grounded, and whose drain electrode is coupled to an inverted bit line BLB, a PMOS transistor P3 whose source electrode is coupled to the bit line BL, a PMOS transistor P4 whose source electrode is coupled to the inverted bit line BLB, whose drain electrode is coupled to the gate electrode of PMOS transistor P3 and whose gate electrode is coupled to the drain electrode of PMOS transistor P3, a PMOS transistor P5 whose source electrode is coupled to the drain electrode of PMOS transistor P3, whose gate electrode is coupled to the gate electrode of PMOS transistor P6 and whose drain electrode is coupled to a data line DL, a PMOS transistor P6 whose gate electrode is coupled to the gate electrode of PMOS transistor P5, whose source electrode is coupled to the drain electrode of PMOS transistor P4 and whose drain electrode is coupled to an inverted data line DLB, an NMOS transistor N1 whose drain and gate electrodes are commonly coupled to the drain electrode of PMOS transistor P6 and whose source electrode is grounded, an NMOS transistor N2 whose gate electrode is coupled to the drain electrode of PMOS transistor P6 and whose source electrode is grounded, a PMOS transistor P7 whose gate and drain electrodes are commonly coupled to the drain electrode of NMOS transistor N2 and whose source electrode is coupled to the power supply voltage, a PMOS transistor P8 whose source electrode is coupled to the power supply voltage and whose gate electrode is coupled to the gate electrode of PMOS transistor P7, an NMOS transistor N3 whose drain electrode is coupled is coupled to the drain electrode of PMOS transistor P8, whose source electrode is grounded and whose gate electrode is coupled to the drain electrode of PMOS transistor P5, an NMOS transistor N4 whose gate and drain electrodes are commonly coupled to the drain electrode of PMOS transistor P5 and whose source electrode is grounded, a PMOS transistor P9 whose source electrode is coupled to the power supply voltage and whose gate electrode is coupled to the drain electrode of PMOS transistor P8, and an NMOS transistor N5 whose gate electrode is coupled to the drain electrode of of NMOS transistor N3, whose drain electrode is coupled to the drain electrode of PMOS transistor P9 and whose source electrode is grounded. A select signal YSEL is applied to the common gate node between PMOS transistors P5 and P6, and-the output is taken from the common drain node between PMOS transistor P9 and NMOS transistor N5.
With the above-described configuration, the PMOS transistors P1 and P2 operate as constant current sources, and the PMOS transistors P3, P4, P5 and P6 operate as a first stage sense amplifier. The PMOS transistors P7 and P8 and the NMOS transistors N2 and N3 operate as a second stage sense amplifier. The PMOS transistor P9 and NMOS transistor N5 operate as an output buffer. The four PMOS transistors P3, P4, P5, and P6 constituting the first stage sense amplifier are equal-sized and can fit within the column pitch of the memory device, thereby avoiding the need for a column selection element, and thereby, in turn, reducing signal propagation delay.
The first stage sense amplifier is selected or activated by grounding the select signal YSEL, thereby turning on the transistors P5 and P6, whereby current is drawn through the transistors P3 and P4 via the bit-line loads. The bit-line loads are low ohmic loads to ensure that the bit lines themselves are always close to the power supply voltage level during a read operation.
Since PMOS transistor P1 and P3 are of equal size, the gate-source voltage V.sub.1 of the PMOS transistor P3 is equal to that of the PMOS transistor P1, so that the respective currents flowing therethrough are equal, i.e., both transistors are in saturation. The same principle applies to the transistors P2 and P4, whose gate-source voltage is represented as V.sub.2.
With the select signal YSEL grounded, the bit line BL and the inverted bit line BLB will both have a voltage of V.sub.1 +V.sub.2. Therefore, the potential of each bit line will both be equal, independent of the current distribution therebetween. Thus, a virtual short circuit exists across the bit line pair BL, BLB. Also, since the bit line voltages are equal, the bit-line load currents will also be equal, as well as the bit-line capacitor currents.
During a read operation, as the selected memory cell draws current, the right-hand leg of the sense amplifier must pass more current than the left-hand leg of the sense amplifier. The difference between these two currents is equal to the current drawn by the selected memory cell (i.e., cell current). The drain currents of the PMOS transistors P5 and P6 are passed to current transporting data line pair DL, DLB, respectively, and the differential data line current is therefore equal to the cell current. This operation is known as current sensing. The cross-coupled structure of the sense amplifier functions as a flip-flop. To prevent unwanted latching of the sense amplifier, the sense amplifier is configured to have a suitable latching margin. However, this latching margin increases bit-line load resistance, increases semiconductor body effect, and decreases the resistance of the short-channel output transistors of the memory device.
The speed of the sensing operation of the above-described current-mode sense amplifier is unaffected by the bit-line capacitance since no differential capacitor discharging is required to sense the data read out of the selected memory cell. Thus, the speed of operation of the memory device is enhanced. A second speed-enhancing feature is provided by the common-mode discharge current pulse i.sub.c from the bit-line capacitors, effectively precharging the sense amplifier as soon as the select signal YSEL is grounded. This second speed-enhancing feature, which can be considered to be a form of dynamic biasing, increases the speed of operation, but does not increase the current consumption of the memory device. Further, since the bit-line voltages are kept equal, the sense amplifier performs an intrinsic equalizing function, thereby eliminating the need for bit-line equalization during a read cycle.
The output of the above-described current-mode sense amplifier can be in current form, or, alternatively, the differential voltage of nodes A and B can be taken as the output to be further amplified by a second stage differential voltage sense amplifier, in which case, the PMOS transistors P3 and P4 operate to propagate voltage only when the nodes A and B are driven to a high level and a low level, respectively. Therefore, if the parasitic capacitance of the data line pair DL, DLB is large and the signal transporting speed thereof is decreased accordingly, the voltages on the data lines DL and DLB only gradually become equal, thus reducing the speed of operation of the output voltage sense amplifier stage.
To summarize the operation of the circuit depicted in FIG. 2, data is read out from a selected memory cell (during a read operation), with the read-out data being transferred to complementary bit lines of a bit line pair, BL, BLB. In order to increase the speed of the read operation, both lines of the bit line pair are maintained as near to the same potential as possible. Only a difference in currents is realized between the nodes C and D. Assume current l1 is drawn through the node C and current l2 is drawn through the node D. The current l2 can be expressed as l1+.DELTA.l. Assuming a binary "1" is read from the selected memory cell during a read operation, the current l2 becomes larger than the current l1, and the voltage V.sub.1 at the node A becomes lower than the voltage V.sub.2 at the node B. Also, since the current l2 is larger than the current l1, the current flowing through the NMOS transistor N3 surpasses that flowing through the NMOS transistor N4. Therefore, the gate-source voltage V.sub.GS1 of the NMOS transistor N3 is greater than the gate-source voltage V.sub.GS2 of the NMOS transistor N4. The voltages V.sub.GS1 and V.sub.GS2 are subsequently applied to the output voltage differential sense amplifier stage.
Therefore, in the conventional semiconductor memory device, PMOS transistors P3 and P4 are chearged to a "high" level and "low" level, respectively. Then, due to signal delays and the large parasitic capacitances along the data lines DL and DLB (as measured at the nodes E and F), the voltages gradually equalize. Also, as the output voltage of the first stage sense amplifier approaches ground potential, the operational speed of the second (output) stage differential voltage sense amplifier is lowered, thereby limiting the overall operating speed of the semiconductor memory device.